首页->【FPGA/CPLD助学小组】

28 0

module siqu_verilog(clk,rst_n,

x_single,y_single);

input clk;

input rst_n;

input x_single;//外部输入信号

output y_single;//加死区后的输出信号

//---------------------------------

reg pwm_r0;

reg pwm_r1;

reg flag;

always @(posedge clk or negedge rst_n)

begin 

if(!rst_n)

begin 

pwm_r0 <= 1'bx;

pwm_r1 <= 1'bx;

end

else begin

pwm_r1 <= pwm_r0;

pwm_r0 <= x_single;

flag = pwm_r0 & (~pwm_r1);

end

end

//---------------------------------

reg[7:0] cnt;//计数器 用来延长 发PWM波周期为100ms 则死区时间为5ms 计数250次

reg R;//检测输入信号的上升沿,当输入信号的上升沿到来R置1

always @( posedge clk or negedge rst_n )

begin

if(!rst_n) begin 

cnt <= 8'd0;

R <= 1'b0;

end

 else if(flag == 1'b1) R <= 1'b1;

else if (R == 1'b1) cnt <= cnt+1'b1;

else if( cnt == 8'd250) 

 begin

cnt <= 8'd0;

R <= 1'b0;

end

 

end

//-----------------------------------

reg y_single;

always @(posedge clk)

if (8'd0 < cnt < 8'd250) y_single <= 1'b0;

   else y_single <= x_single;

//----------------------------------

endmodule 


楼主可见