首页->【FPGA/CPLD助学小组】

480 4

我想在fifo里写入递增的数据,然后通过LED灯显示出来。可是led总是低电平  怎么回事啊

`timescale 1ns / 1ps

module my_fifo(
    clk,rst_n,
    led
   );
input clk;  
input rst_n; 

output[7:0]led;
reg[24:0] cntwr; 
wire[7:0] wrf_din; 
wire wrf_wrreq;
always @(posedge clk or negedge rst_n)
 if(!rst_n) cntwr <= 25'd0;
 else cntwr <= cntwr+1'b1;
assign wrf_wrreq = (cntwr >= 25'h1fffffe) && (cntwr <= 25'h1ffffff); //FIFO写有效信号
//------------------------------------------
reg[7:0] wrf_dinr; 
always @(posedge clk or negedge rst_n)
 if(!rst_n) wrf_dinr <= 8'd0;
 else if((cntwr >= 25'h1ffffe) && (cntwr <= 25'h1ffffff))
  wrf_dinr <= wrf_dinr+1'b1; 
  
assign wrf_din = wrf_dinr;
reg led_en;
reg data_en;
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
          led_en=1'b0;
          data_en=1'b0;
          end
else if(wrf_dinr>1'b0)
        begin
         led_en=1'b1;
         data_en=1'b1;
        end 
reg led_enr1,led_enr2;
 
always @(posedge clk or negedge rst_n)
 if(!rst_n) begin
   led_enr1 <= 1'b1;
   led_enr2 <= 1'b1;
  end
 else begin
   led_enr1 <= led_en;
   led_enr2 <= led_enr1;
  end
assign led_rdreq = led_enr1 & ~led_enr2; 
//---------------------------------------------------------
reg[7:0] led_r;  
always @ (posedge clk or negedge rst_n)
 if(!rst_n) begin
  
  led_r<=8'd0;
  end
 else if(data_en) begin
            if(led_en)     
            led_r<=tx_data;
            end
           
           
assign led = led_r;
wire[7:0]tx_data;

fifo fifo_inst (
               .clock ( clk ),
               .data ( wrf_din ),
               .rdreq ( led_rdreg ),
               .wrreq ( wrf_wrreq ),
               .q ( tx_data )
               );
 

endmodule
 
楼主可见

  1. vividbearylz 4#

    仿真一下容易发现问题

  2. Manutd 3#
    回复:wswxdw

    我用Quartus 仿真了,结果好像有点问题,可错在哪里啊

    报错是什么情况

  3. wswxdw 2#

    我用Quartus 仿真了,结果好像有点问题,可错在哪里啊

  4. CrazyBingo 1#

    你敢不敢自己modelsim一下下啊?