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在仿真一个很简单的程序时,出现以下问题:

Vivado Simulator 2014.2

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Running: D:/Xilinx/Vivado/2014.2/bin/unwrapped/win64.o/xelab.exe --debug typical --relax -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot simu_behav --prj D:/Xilinx/Vivado/mutiplication/mutiplication.sim/sim_1/behav/simu.prj xil_defaultlib.simu xil_defaultlib.glbl 

Multi-threading is on. Using 2 slave threads.

Determining compilation order of HDL files.

INFO: [VRFC 10-165] Analyzing Verilog file "D:/Xilinx/Vivado/mutiplication/mutiplication.srcs/sim_1/new/simu.v" into library xil_defaultlib

INFO: [VRFC 10-311] analyzing module simu

INFO: [VRFC 10-165] Analyzing Verilog file "D:/Xilinx/Vivado/2014.2/data/verilog/src/glbl.v" into library xil_defaultlib

INFO: [VRFC 10-311] analyzing module glbl

Starting static elaboration

ERROR: [VRFC 10-2063] Module <multplication> not found while processing module instance <simu> [D:/Xilinx/Vivado/mutiplication/mutiplication.srcs/sim_1/new/simu.v:27]

ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

希望大家能够帮忙了,谢谢了。

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