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大家好:

    Xilinx 的IDELAY2 和ODELAY2 怎么使用?谁有例程能否共享学习一下??

我在工程中例化之后编译一直报错。

还有    (*IODELAY_GROUP=<iodelay_group_name>*) 这个怎么设置》?<iodelay_group_name>怎么查看才能确定位置啊?

报的错误为:

  [Place 30-640] Place Check : This design requires more ODELAYE2 cells than are available in the target device. This design requires 1 of such cell types but no compatible site is available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.



谢谢!!!


FPGA 为 A7- 100T

楼主可见

  1. wzheng 1#

    <iodelay_group_name> 是你自己的区分名字,和其他(* *)用法的 参数一样加个"your iodelay_group_name"即可