首页->【Verilog HDL 与FPGA的认知火花】

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vlib cyclone
vmap cyclone {D:/Program Files (x86)/Altera/modelsim_ase/altera/verilog/cycloneiii}    
vlib lib

#add library

vmap lib {D:/Program Files (x86)/Altera/modelsim_ase/altera/verilog/altera_mf}
vlib work
vmap work   

#compile varilog source files
vlog  channel_dram.v

#RCV MODULE
vlog Usound_receive.v
#vlog CHANNEL_REC_ctr_old.v
vlog dyn_filter_dem.v
#test bench
vlog Usound_receive_sim.v
#IP CORE
vlog FOCUSPARA_ram_ch1.v

#sim
vsim -L {D:/Program Files (x86)/Altera/modelsim_ase/altera/verilog/cycloneiii} -L {D:/Program Files (x86)/Altera/modelsim_ase/altera/verilog/220model}  -L {D:/Program Files (x86)/Altera/modelsim_ase/altera/verilog/altera_mf} -wlf Usound_receive_sim_pre.wlf  -novopt work.Usound_receive_sim
#add all the waves to design
add wave -r /*
#run
run -all

楼主可见

  1. shwnyoo 1#

    通过使用仿真脚本进行仿真,可以达到事半功倍之效果