首页->【Verilog HDL 与FPGA的认知火花】

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set commentA=/*
set dsn=Dsn By :
set dsnName=*******Winyoo_shiy******************
set func=FunctionDesp:
set funcDetail=*******put your descript**************
set Date=GenDate:
set DateDetail=*******put your date*****************
set place=Location:
set location=*********put location here**************    
set Rls=ReleaseDate:      
set RlsDate=*********put rls date*******************
set copyright=Open  Right

set /p arg=pls input FileName of Verilog(not include .v):
set  fileName=*********%arg%.v*******************
set commentB=*/

set  path=F:\shwnyoo\StuDat\Suda\Doc\S.Winyoo
:: wr info into ***.v
echo %commentA%>> %path%\%arg%.v
echo %dsn%>> %path%\%arg%.v
echo %dsnName%>> %path%\%arg%.v
:: function and introdution
echo %func%>> %path%\%arg%.v
echo %funcDetail%>> %path%\%arg%.v
:: date &debug
echo %Date%>> %path%\%arg%.v
echo %DateDetail%>> %path%\%arg%.v
:: addr
echo %place%>> %path%\%arg%.v
echo %location%>> %path%\%arg%.v
::Release
echo %Rls%>> %path%\%arg%.v
echo %RlsDate%>> %path%\%arg%.v
:: copyright info
echo %copyright%>> %path%\%arg%.v
::fileName
echo %fileName%>> %path%\%arg%.v
echo %commentB%>> %path%\%arg%.v

程序运行结果:
图片.png

楼主可见

  1. shwnyoo 1#

    bat 文件与verilog 文件相互学习